When information is transmitted over a communications system, it is often necessary to selectively route signals between various signal sources and receivers. In a general case, if signals are to be transmitted between "i" sources and "j" receivers, an i by j matrix is created which has a total of i.j crosspoints. A switch is needed at each crosspoint to open or close the circuit between a given source and a given receiver. In an extreme case within the television industry, a system having 65,536 crosspoints is used to route video encoded signals between 256 television cameras and 256 receivers.
Routing systems constructed according to the prior art have required dedicated control lines for each switch. Such prior art systems are disadvantageous in that the necessary interconnections become increasingly difficult to make as matrix size increases. Another disadvantage of prior art routing systems is that the amount of current needed to operate each switch remains relatively constant regardless of whether or not the switch conducts a signal to a receiver.
In accordance with the illustrated preferred embodiment of the present invention, a monolithic switch comprises two latches, a differential delay circuit, a switch, and several buffer amplifiers. A data signal received on a data line is loaded into the first latch when a simultaneous strobe signal is received on a strobe line. The crosspoint switch is armed to close and cause the signal to be routed to the selected output port. The data signal is passed from the first latch to the second latch, and a change of state of the crosspoint becomes possible, when a clock signal is received at the clock input of the second latch. Thus, the next desired state of each switch can be preset individually and asynchronously and the actual states of all the switches can be changed simultaneously, e.g., during a vertical interval if video signals are being routed. The total number of control lines needed to control all of the switches in the routing system is minimized since a common clock line is used, the switches in each row utilize a common data line, and the switches in each column utilize a common strobe line.
The data signal received by the second latch is coupled to the switch through the differential delay circuit which allows the switch to turn on more rapidly than it turns off. Thus, the routing system is of the make before break type, which eliminates voltage spikes in the output signal due to the output transistor turning off before another switch on the output bus turns on.
One output signal of the differential delay circuit commands the switch either to interrupt the incoming signal, or to conduct it to the buffer amplifier and from there, to a receiver. Another output signal of the differential delay circuit causes the current source of the buffer amplifier to enter a low current idle state if the incoming signal is to be interrupted. In this manner, a reduction in power consumption of approximately 8:1 is achieved when the input signal is interrupted.
Since a large signal routing system may include many thousands of these switches, the switches are manufactured in a monolithic structure to minimize size and power requirements. The problem in any monolithic structure is the inability to generate lateral PNP devices with a high beta. To overcome this problem the currents must be well defined to make the offsets work out correctly. A standard Darlington transistor pair configured as a current mirror may be used. However, this configuration alone does not adequately compensate for the low beta of lateral PNP transistors. Therefore the Darlington configurtion is modified by inserting a multi-collector transistor between the collectors of the Darlington transistors. One collector is diode connected to the base and the other is returned to a potential source. This provides accurate current representation at the output of the current mirror.